Table of Contents

• A. ABOUT THE AUTHOR
• B. Preface
• 1. Introduction to PLLs
• 2. Mixed-Signal PLL Building Blocks
• 3. Mixed-Signal PLL Analysis
• 4. PLL Performance in the Presence of Noise
• 5. Design Procedure for Mixed-Signal PLLs
• 6. Mixed-Signal PLL Applications Part 1: Integer-N Frequency Synthesizers
• 7. Mixed-Signal PLL Applications Part 2: Fractional-N Frequency Synthesizers
• 8. Mixed-Signal PLL Applications Part 3: Miscellaneous Applications
• 9. Higher-Order Loops
• 10. Computer-Aided Design and Simulation of Mixed-Signal PLLs
• 11. All-Digital PLLs (ADPLLs)
• 12. Computer-Aided Design and Simulation of ADPLLs
• 13. The Software PLL (SPLL)
• 14. The PLL in Communications
• 15. Searching PLL Integrated Circuits
• 16. The Pull-in Process
• B. The Laplace Transform
• 18. Digital Filter Basics
• 19. Measuring PLL Parameters
• A. References
• B. CD-ROM WARRANTY

• figure (284)
• table (6)

Expanded Table of Contents

• A. ABOUT THE AUTHOR
• B. Preface
• 1. Introduction to PLLs
  • Operating Principles of the PLL
  • Historical Background
  • Classification of PLL Types
• 2. Mixed-Signal PLL Building Blocks
  • Block Diagram of the Mixed-Signal PLL
  • A Note on Phase Signals
  • Building Blocks of Mixed-Signal PLLs
  • Phase Detectors
  • Loop Filters (First Order)
  • Controlled Oscillators
  • Down Scalers
• 3. Mixed-Signal PLL Analysis
  • PLL Performance in the Locked State
  • The Mathematical Model for the Locked State
  • A Definition of Transfer Functions
  • Transient Response of the PLL in the Locked State
  • Steady-State Error of the PLL
  • The Order of the PLL System
  • PLL Performance in the Unlocked State
  • Mathematical Model for the Unlocked State
  • Key Parameters of the PLL
  • Optimizing the Lock Process
  • In-Lock detectors
• 4. PLL Performance in the Presence of Noise
  • Sources and Types of Noise in a PLL
  • Defining Noise Parameters
  • The Impact of Noise on PLL Performance
  • Pull-in Techniques for Noisy Signals
• 5. Design Procedure for Mixed-Signal PLLs
• 6. Mixed-Signal PLL Applications Part 1: Integer-N Frequency Synthesizers
  • Synthesizers in Wireless and RF Applications
  • Integer-N Frequency Synthesizers without Prescalers
  • Integer-N Frequency Synthesizers with Prescalers
  • Extending the Frequency Range with Mixers and Frequency Multipliers
  • Case Study: Designing an Integer-N PLL Frequency Synthesizer
  • Single-Loop and Multi-Loop Frequency Synthesizers
  • Phase Noise and Spurs in Integer Frequency Synthesizers
• 7. Mixed-Signal PLL Applications Part 2: Fractional-N Frequency Synthesizers
  • Realization of Fractional Divider Ratios
  • Analog Spur Reduction Techniques
  • Digital Spur Reduction Techniques
  • Reviewing the ΣΔ Modulator
  • The Design Procedure for ΣΔ Modulators
  • Spurs, Fractional Spurs, and Subfractional Spurs
  • Alternative ΣΔ Modulators: The MASH Converter
• 8. Mixed-Signal PLL Applications Part 3: Miscellaneous Applications
  • Retiming and Clock Signal Recovery
  • Motor-Speed Control
• 9. Higher-Order Loops
  • Motivation for Higher-Order Loops
  • Analyzing the Stability of Higher-Order Loops
  • Designing Third-Order PLLs
  • Designing Fourth-Order PLLs
  • Designing Fifth-Order PLLs
  • The Key Parameters of Higher-Order PLLs
• 10. Computer-Aided Design and Simulation of Mixed-Signal PLLs
  • Overview
  • Quick Tour
  • Simulations with and without Averaging
  • Simulations with Noisy Reference Signals
  • Displaying Waveforms of Tri-State Signals
  • Getting Help
  • Shaping the Appearance of Graphic Objects
  • Suggestions for Case Studies
• 11. All-Digital PLLs (ADPLLs)
  • ADPLL Components
  • Examples of Implemented ADPLLs
  • Theory of a Selected Type of ADPLL
  • Typical ADPLL Applications
  • Designing an ADPLL
• 12. Computer-Aided Design and Simulation of ADPLLs
  • Designing the ADPLL
  • Simulating ADPLL Performance
  • Case Studies on ADPLL Behavior
• 13. The Software PLL (SPLL)
  • The Hardware-Software Trade-off
  • The Feasibility of an SPLL Design
  • SPLL Examples
• 14. The PLL in Communications
  • Types of Communications: Baseband and Bandpass
  • Amplitude Shift Keying
  • Phase Shift Keying
  • Frequency Shift Keying
  • Quadrature Amplitude Modulation (QAM)
  • The Role of Synchronization in Digital Communications
  • Digital Communications Using BPSK
  • Digital Communications Using QPSK
  • Digital Communications Using QAM
  • Digital Communications Using FSK
  • Digital Communications in Mobile Phones
  • Bandwidth Efficiency, Bit Error Rate (BER), and the Signal Power Efficiency of Digital Modulation Schemes
• 15. Searching PLL Integrated Circuits
• 16. The Pull-in Process
  • The Simplified Model for the Pull-in Range Δω p of the LPLL
  • A Simplified Model for the Pull-in Time T p of the LPLL
  • The Pull-in Range Δω p of the DPLL
• B. The Laplace Transform
  • Transforms Are the Engineer’s Tools
  • Laplace Transform Is the Key to Success
  • A Numerical Example of the Laplace Transform
  • Some Basic Properties of the Laplace Transform
  • Using the Table of Laplace Transforms
  • Applying the Laplace Transform to Electric Networks
  • Closing the Gap Between the Time Domain and the Complex Frequency Domain
  • Networks with Nonzero Stored Energy at t = 0
  • Analyzing Dynamic Performance by the Pole-Zero Plot
  • A Simple Physical Interpretation of “Complex Frequency”
• 18. Digital Filter Basics
  • The Transfer Function H(z) of Digital Filters
  • IIR Filters
  • FIR Filters
• 19. Measuring PLL Parameters
  • Measurement of Center Frequency f 0
  • Measurement of VCO Gain K 0
  • Measurement of Phase-Detector Gain K d
  • Measurement of Hold Range Δω H and Pull-in Range Δω P
  • Measurement of Natural Frequency ω n, Damping Factor ζ, and Lock Range Δω L
• A. References
• B. CD-ROM WARRANTY
  • LIMITED WARRANTY